Polycrystalline Silicon PID Testing: Potential Induced Degradation Evaluation for Photovoltaic Modul

Polycrystalline silicon PID (Potential Induced Degradation) testing is a critical reliability evaluation that measures how photovoltaic modules withstand sustained voltage stress under humid, high-temperature conditions, in accordance with IEC TS 62804-1. This article explains the degradation mechanism, sample requirements, test methods, acceptance criteria, and practical applications of PID testing for polycrystalline silicon solar modules.

Technical Overview

Potential Induced Degradation (PID) is a failure mechanism in crystalline silicon photovoltaic (PV) modules caused by leakage currents that flow between the solar cells and the grounded module frame under system operating voltages. In large PV arrays, modules positioned at the end of a string can experience a potential difference of several hundred to over one thousand volts relative to ground. This sustained electric field drives ion migration, most notably sodium ions (Na+) released from the soda-lime cover glass, through the encapsulant and toward the cell surface. The accumulated ions create localized shunts across the p-n junction, which appear as characteristic dark patterns in electroluminescence (EL) imaging and manifest as significant reductions in maximum power output.

Polycrystalline (multi-crystalline) silicon modules, particularly those built on p-type wafers with conventional encapsulant materials, have historically shown significant susceptibility to PID. Power losses exceeding 30% have been documented in affected installations, especially in hot and humid climates. PID testing therefore has become an essential element of module qualification, material selection, and power plant risk management, with the internationally recognized test procedure defined in IEC TS 62804-1. The test is also referenced within the extended stress sequences of the IEC 61215 series, which governs design qualification and type approval of terrestrial PV modules.

Testing Samples

Full-Size Polycrystalline Silicon PV Modules

Standard commercial modules, typically 60-cell or 72-cell configurations based on p-type multi-crystalline silicon cells, represent the primary test specimens. Modules should be complete assemblies with frames, junction boxes, and cables intact, as the frame grounding path is integral to the PID mechanism. One or two modules are generally tested per condition depending on the test plan and statistical requirements.

Mini-Modules and Laminate Samples

Reduced-format samples, such as 2x2 or 4x4 cell laminates with or without frames, are widely used for rapid material screening and research purposes. These samples shorten preparation time and allow parallel comparison of multiple encapsulant, glass, and anti-reflection coating combinations during product development.

Material-Level Specimens for Root Cause Analysis

Individual cells, encapsulant films (EVA or POE), and cover glass samples may be evaluated using surface analysis techniques to identify sodium contamination, ion mobility characteristics, or coating defects when investigating the root cause of PID susceptibility in a specific module design.

Testing Items

PID evaluation combines electrical, imaging, and safety measurements performed before, during, and after voltage stress exposure. Typical test items include:

• Maximum power (Pmax) measurement at Standard Test Conditions (STC: 1000 W/m², 25°C, AM 1.5G) before and after stress, with degradation percentage calculated as the key result
• Electroluminescence (EL) imaging to visualize shunted cell regions, grid patterns, and checkerboard or edge-adjacent darkening characteristic of PID
• Dark I-V characterization and shunt resistance measurement to quantify junction leakage
• Leakage current monitoring during voltage stress as an indicator of ionic transport activity
• Insulation resistance and wet leakage current testing to confirm electrical safety after stress
• Visual inspection in accordance with IEC 61215 criteria to detect bubbles, delamination, or discoloration induced during the test

Testing Methods

Damp Heat Chamber Method (IEC TS 62804-1)

The most widely applied procedure places the module in an environmental chamber at 85°C and 85% relative humidity while applying a negative bias of the rated system voltage, commonly -1000 V or -1500 V, between the shorted module terminals and the grounded frame. The standard exposure duration is 96 hours, and extended durations of 192 hours or longer are frequently specified for demanding applications. The combination of heat, humidity, and voltage accelerates the ion migration that drives PID in field operation.

Surface-Conductive Method (Aluminum Foil or Wet Cloth)

As an alternative to the chamber method, a conductive medium such as aluminum foil, foil with water film, or a wet cloth is pressed against the module front surface and connected to one voltage terminal, while the cell circuit is held at the opposite potential. This method concentrates the stress on the front interface between glass, encapsulant, and cells and offers faster execution without a full climate chamber, though it represents a different stress distribution than full-module damp heat exposure.

Combined and Sequential Stress Testing

For comprehensive qualification, PID stress is often combined with thermal cycling (TC 200 or TC 50) and damp heat (DH) sequences described in IEC 61215, or extended to 600-hour damp heat exposures. These combined protocols evaluate whether PID-related shunts interact with other degradation modes across the module lifetime.

Pass Criteria and Result Evaluation

According to IEC TS 62804-1, a module passes the test when the relative degradation of maximum power does not exceed 5% after the specified stress, with no major visual defects and continued compliance with insulation and wet leakage requirements. EL images are compared before and after stress to confirm the absence of extensive shunting. A recovery test, in which the module is stored at STC or subjected to forward bias, may be performed to distinguish recoverable PID-shunting effects from permanent degradation.

Applications

PID testing for polycrystalline silicon modules serves multiple purposes across the photovoltaic value chain:

• Product certification and type approval, where PID resistance evidence is required by buyers and referenced within IEC 61215 extended test programs
• Encapsulant and material selection, comparing EVA formulations, POE-based encapsulants, quartz-rich or barrier glasses, and cell anti-reflection coating chemistries for anti-PID performance
• Tender and bankability documentation for utility-scale power projects, where demonstrated PID resistance supports long-term energy yield warranties and financial models
• Incoming quality control for module procurement, verifying that delivered batches match the qualified design
• Failure analysis and field diagnostics, reproducing PID in the laboratory to confirm root causes observed in affected power plants and to validate remediation measures such as charge-equalization devices
• Research and development of PID-resistant cell technologies, including emitter designs, silicon nitride coating optimization, and grounding schemes

FAQ

What causes PID in polycrystalline silicon modules?

PID is driven by the system voltage between the cells and the grounded frame. Under humidity and elevated temperature, sodium ions from the cover glass migrate through the encapsulant to the cell surface, shunting the p-n junction and reducing power output. The crystalline grain boundaries and defects in polycrystalline wafers can provide additional leakage pathways, making these modules historically more sensitive than high-quality monocrystalline designs.

How long does a standard PID test take?

A standard IEC TS 62804-1 test applies voltage stress for 96 hours at 85°C and 85% relative humidity. Including initial characterization, final measurement, and recovery stabilization, a complete evaluation typically requires approximately one to two weeks.

Is PID reversible?

In many cases, yes. PID caused by sodium shunting (often called PID-s) is largely recoverable when the module is operated under reversed stress, kept at elevated temperature without bias, or treated with charge-equalization equipment. However, prolonged exposure leads to permanent degradation, so early detection and prevention are strongly preferred.

What is the pass criterion for PID testing?

The widely accepted criterion defined in IEC TS 62804-1 is a maximum power degradation of no more than 5% after the stress exposure, combined with the absence of major visual defects and continued compliance with insulation safety requirements. Many project developers impose stricter internal limits, such as 2% or 3%, for higher-voltage systems.

How can PID be prevented?

Effective countermeasures include using PID-resistant encapsulants such as POE, applying anti-PID cell coatings, selecting glass with low sodium mobility, adopting frame designs that reduce leakage paths, grounding the negative pole of the array, and installing charge-equalization devices. These measures should be validated through laboratory PID testing before mass production.

Where can polycrystalline silicon PID testing be performed?

PID testing should be conducted by accredited third-party laboratories or in-house laboratories equipped with climate chambers, high-voltage bias supplies, solar simulators calibrated to IEC 60904-9, and EL imaging systems, ensuring that results conform to IEC TS 62804-1 and are accepted by international buyers and certification bodies.