IC Substrate Dimensional Stability Expansion Testing

IC substrate dimensional stability expansion testing measures the coefficient of thermal expansion (CTE), glass transition temperature (Tg), and dimensional change behavior of IC package substrates under thermal and moisture stress. Accurate expansion data is critical for substrate material qualification, fine-line registration control, warpage prediction, and solder joint reliability in advanced packaging such as FCBGA, SiP, and 2.5D/3D architectures. Our laboratory provides professional CTE and dimensional stability testing services compliant with IPC-TM-650, ASTM, and JEDEC standards.

Technical Overview

IC package substrates serve as the electrical and mechanical interconnect between the semiconductor die and the printed circuit board. As line and space geometries shrink to 10 μm and below in advanced packaging, even minute substrate expansion or shrinkage can cause layer-to-layer misregistration, via breakage, and solder joint failure. Dimensional stability expansion testing quantifies how a substrate material or finished panel expands, contracts, or deforms when subjected to thermal cycling, reflow simulation, and moisture absorption.

The core technical concern is the mismatch in coefficient of thermal expansion among the silicon die (approximately 2.6 ppm/°C), copper circuitry (about 17 ppm/°C), substrate core and buildup layers (typically 10–17 ppm/°C in-plane), and the assembly board. Excessive or anisotropic expansion generates internal stress, panel warpage, and ball grid array coplanarity defects. Systematic expansion testing therefore underpins material selection, design rule definition, and reliability qualification for every generation of IC substrate.

Testing Samples

Core Substrate Materials (CCL)

Copper-clad laminate panels based on bismaleimide triazine (BT) resin, high-Tg epoxy, modified epoxy, or low-Dk/Df systems reinforced with glass cloth. Specimens are typically prepared at 3–6 mm square or rectangular strips for through-thickness and in-plane measurement.

Buildup Film Materials (ABF)

Ajinomoto buildup film and equivalent insulating dielectric films used for sequential build-up layers. These materials exhibit relatively high out-of-plane CTE, making z-axis expansion characterization essential for microvia reliability.

Prepreg and Laminate Composites

B-stage prepreg sheets and multilayer laminate stacks used in substrate fabrication, evaluated for post-lamination shrinkage and flow-induced dimensional change.

Finished Multilayer Substrates

Production-representative substrate panels with benchmark marks or tooling holes, tested for absolute dimensional accuracy, layer-to-layer registration, and warpage before and after simulated assembly stress.

Testing Items

Our dimensional stability and expansion test portfolio covers the full range of parameters required by substrate designers and reliability engineers:

• In-plane CTE below Tg (α1) and above Tg (α2) in x and y directions
• Out-of-plane (z-axis) CTE and total thickness expansion
• Glass transition temperature by TMA
• Total thermal expansion percentage over defined temperature ranges, such as 50–150°C, 50–200°C, and 50–260°C
• Post-etch and post-lamination dimensional change (ppm or mils per 100 mm) relative to phototool reference
• Moisture absorption expansion after 85°C/85%RH conditioning or immersion
• Dimensional change after simulated reflow at 260°C peak per JEDEC J-STD-020
• Warpage, twist, and coplanarity of finished substrates under thermal load
• Anisotropy ratio between machine and transverse directions

Testing Methods

Thermomechanical analysis (TMA) is the primary method for expansion measurement, performed per IPC-TM-650 method 2.4.24 and ASTM E831. A calibrated quartz expansion probe applies a minimal static load to the specimen while a programmed furnace ramps temperature at 5 or 10°C/min under nitrogen purge. A two-scan protocol is applied: the first scan erases thermal history and relieves residual stress from lamination, while the second scan provides the reported CTE and Tg data.

In-plane and panel-level dimensional stability are evaluated with non-contact optical and vision measurement systems. Key procedural steps include:

• Specimen pre-baking at 105–125°C to remove absorbed moisture, followed by conditioning at 23±2°C and 50±5% RH for 24 hours
• Establishment of baseline coordinates using benchmark marks, tooling holes, or laser-drilled fiducials
• Exposure to defined stress: thermal cycling, convection reflow simulation, pressure cooker testing, or 85°C/85%RH dwell
• Post-stress re-measurement and calculation of dimensional change in ppm along both axes
• Warpage evaluation using shadow moiré, laser displacement profilometry, or 3D optical scanning across the temperature profile

Test reports include full expansion curves, α1/α2 values, Tg, total expansion percentages, directional anisotropy, and statistical averages across replicate specimens, giving designers directly usable input for finite element warpage models.

Applications

Dimensional stability expansion testing supports every stage of the IC substrate product lifecycle:

• Incoming material qualification for BT core and ABF buildup film suppliers
• CTE matching and warpage prediction for flip-chip BGA and high-density FCBGA substrates
• Layer-to-layer registration and etching compensation studies for fine-line circuit formation
• Reliability qualification of memory module substrates, SiP packages, and embedded die designs
• 2.5D/3D packaging interposer and bridge substrate development
• Automotive-grade substrate qualification under extended thermal cycling requirements
• Failure analysis of warpage, delamination, and solder joint cracking in returned units

FAQ

What is the difference between α1 and α2 CTE? α1 is the coefficient of thermal expansion below the glass transition temperature, representing the operating region of the substrate, while α2 is the steeper expansion above Tg, relevant to reflow and other high-temperature processes. Both values are needed to predict behavior across the full assembly thermal range.

Why must z-axis expansion be controlled in IC substrates? Out-of-plane expansion stresses plated through-holes and microvias during reflow. Excessive z-axis CTE above Tg is a leading cause of via barrel cracking and interfacial separation in buildup structures.

Which standards govern this testing? Commonly applied standards include IPC-TM-650 method 2.4.24 for TMA, ASTM E831 for linear expansion by TMA, IPC-4101 for laminate qualification, and JEDEC J-STD-020 for reflow simulation conditions.

What sample size and quantity are required? TMA specimens are typically 3–6 mm with thickness of 0.3–1.6 mm, with a minimum of three replicates per condition. Panel-level dimensional stability testing requires production-format panels with reference fiducials, typically 100 mm square or larger.

How long does testing take? Standard TMA CTE and Tg measurement is typically completed within 3–5 working days, while full dimensional stability programs including moisture conditioning and reflow simulation may require 1–2 weeks depending on the test matrix.